Huff & Puff Oscillator Stabiliser Frequency Simulator |

Written by Hans Summers |

Friday, 04 September 2009 21:53 |

## The SimulatorProvided you have Java enabled on your browser (not javascript, that's different), you should now see a 640 x 400 window above this text, displaying a simulation run with a set of default circuit parameters. This work was written in January 2002. It is NOT FINISHED, and it is NOT PERFECT either, not by a long way. It is the first time I have ever programmed in Java and I'm not great at it. One problem is that when you type a value in one of the white entry boxes, you must press the ENTER key before pressing TAB to move to the next field. Immediately you press ENTER, the model recalculates. You might also notice various other problems with the display and calculated measurements. If you know Java then please look at the source code and suggestions would be appreciated. The graph line shows the frequency variation during 2000 stabiliser correction periods (initial default number). The VFO frequency starts off at the entered target value and converges rapidly to the nearest lock point. This model simulates the "Fast" Huff & Puff stabiliser as developed initially by Peter Lawton G7IXH. See the Huff & Puff reference library for more information. The VFO frequency, crystal reference frequency, number of shift register stages, etc etc can all be adjusted to investigate the effect on the ripple, step size, etc. At the lower left of the window you'll see some calculated and measured values. The measured values are taken on the last 400 (default "measurement samples" value) iterations of the run. ## Original "slow" Stabiliser SimulationNote that this simulator can also be used to model the old "slow" type of stabiliser, as originally developed by Klaas Spaargaren PA0KSB and subsequently refined by others. In order to do this, just set the number of delay stages to 1. You will need to increase the number of VFO division stages accordingly. Increase the number of VFO division stages by 1 for every power-of-2 reduction in the number of delay stages. E.g. to change from 256 stages to 128, increase the VFO division factor from 8 to 9. This is actually quite a good example, since 128 stages requires just one 4517 IC, whereas 256 require two IC's for a rather marginal improvement in performance. As a starting point, try changing the following parameters: VFO division stages = 16 It is immediately apparent how much of an improvement the "fast" design is, in terms of the drift rate it is capable of correcting, and the amount of frequency ripple. (Note: There appears to be a problem with the measurement of lock frequency, in this mode: it is too small by a factor of 2). ## Extreme Huff & PuffI once designed a MASSIVE delay line consisting effectively of 1,048,576 stages, yes that's over 1 million stages of shift register. The basis for this a memory chip, an easily available fast static RAM, 128K x 8 bit size. The 8 bits were to be read out and rewritten in a rolling sequence, with bits connected to the next in line such that it became line a rotating drum 8 tracks on, or rather a single spiral track from top to bottom. I went as far as getting all the parts for this design but never had time to build it (yet). It is also worth noting that the relation between number of stages and improved performance is not linear. I have a hunch (but can't prove theoretically) that the improvement in ripple performance is proportional to a logarithm of the number of delay stages. ## Experiment with different Mark/Space ratiosIn several of the reference library articles, mention is made of the requirement for a crystal reference oscillator having exact 50% duty ratio. The importance of this is repeatedly stressed. However, most canned crystal oscillator modules deliver 60:40, so need to be followed by a divide-by-2 stage to get 50:50. Reducing the frequency by a factor of 2 harms the ripple too: in general the higher reference frequency you can use, the better. So, is it true? Do you really need a 50:50 oscillator? I decided to use the Java simulator to find out. The answer is NO! I believe all those people insisting on 50% had not tried 60:40 and the lack of an accurate theoretical description leads to the wrong assumption. Above are the results of my experiment. It can be seen that the stabiliser remains unconditionally locked and stable across a wide range of mark/space ratios. Certainly, anywhere between 30 and 70% is entirely acceptable. The frequency ripple is definitely affected and shows an interesting periodicity with respect to the mark/space ratio. 30% is as good as 50%, and 60:40 for example, gives the worst ripple. So, from these results it would appear that the authors were wrong, and 50:50 isn't required. The question now is, do we do it? If you are a purist, then yes. Otherwise, I feel that the gain in using a 50% duty cycle (in terms of low ripple) is offset, probably exactly, by the loss by effectively halving the reference frequency. And if you don't bother to divide-by-2 for the exact 50% cycle, then you save on component count. Conclusion: don't worry about duty cycle! But, who can explain this and the observed periodicity with a proper theoretical description! |

Last Updated on Monday, 19 January 2015 05:25 |