1-chip stabiliser Print
Written by Hans Summers   
Friday, 04 September 2009 22:13

Here's a 1-chip stabiliser! Yes, it really is possible to make a Huff Puff stabiliser using a single 74HC4060! This ultra-simple design doesn't include the VFO of course. For development purposes, I re-used the same 74HC74 VFO of the 2- and 3-chip projects, but opened the Huff Puff correction loop such that it was unstabilised.

Now for some theory about its operation:

Here the VFO is at 96Hz for the sake of argument. The differentiator output (DIF) produces a very short spike on the 0 to 1 transition of Q. Here I have drawn 2 such pulses. When the spike is not present, the 10K resistor drags the signal from the VFO down, via the 1N4148 diode. However when the spike occurs, at that instant if the VFO signal is logic 1 (high) then the 74HC4060 counter is reset. In my drawing, the first DIF spike produces a RES, because I assume that the VFO is 1 at that instant. Then Q becomes 0 again. The next DIF spike I am saying occurs momentarily when VFO happens to be 0. So it produces no RES, and Q becomes 1.

A slight complication is that in this 2nd case we have to wait twice as long for the next DIF pulse, because Q goes to 0 naturally at the next occasion and doesn't cause a DIF pulse until it tries to go to 1 again. I was worried that this variable clocking would not permit lock, so I wrote a spreadsheet simulation which showed that it does work. I wasn't able in my mind to decide that, I had to prove it "experimentally" in the spreadsheet (see result, right).

So you can see that between DIF pulses the VFO cycles don't cause a counter reset.

When the VFO alignment is such that it is always 0 on the DIF pulse, the counter will never reset, and the duty cycle at Q will be 50% and it will raise the integrator voltage towards its max 2.5V. Varicap capacitance decreases and the VFO is adjusted upwards.

Conversely if the VFO alignment is such that it is always 1 when the DIF pulse occurs, then the counter will always reset every time, and the duty cycle at Q will be 0% (nearly, but in reality a tiny little bit over 0% due to the time taken to generate the reset pulse). In this case the integrator voltage moves down, capacitance increases and the VFO moves downwards.

The stable situation is when the DIF pulses find the VFO at 1 or 0 such that the Q duty cycle is 25%, which drives the integrator neither up nor down on average over many pulses. (That isn't quite on alternate cycles, because of the twice-as-long thing I described).

The movement of the VFO in always-1 and always-0 situations is such that it moves to the lock point, whereupon the stable condition occurs and we're happy.

And in practice...

...it works just as it should! I wrote the above theoretical explanation before I had time to actually build a real device. There was originally a slight difference, in the way the VFO signal and the differentiator spike were combined. I had used two diodes and a resistor to +5V. This did NOT work, it seemed that in some way the diodes behaved as a charge-pump. Apart from this minor problem, everything worked just as expected.

To the right, here's my constructed 1-chip VFO, "ugly" style as for the other projects. The resistor at the bottom left of the picture leads to the VFO signal to be stabilised, while the one leading off the picture at the top left goes to the VFO varicap and applies the correction signal from the integrator.

The stabiliser is less efficient than the previous 2- and 3-chip designs, and I found that it was necessary to increase the frequency lock size to allow a stable lock. The component choices were in some cases very critical, for example the exact balance of resistors in the VFO / Differentiator pulse combiner. The differentiator time constant (22pF and 10K) is also important: it must be made as short as possible while still allowing a lock.

I did find that again, the choice of integrator resistor was reasonably non-critical. It was necessary to decrease the size of the resistor to the varicap from 1M to 470K.

Notice that the two capacitors are no longer equal: now they are 100uF and 220uF. This is because the output of the integrator is now 0 - 2.5V not 0 - 5V as before. Therefore a starting value for the integrator should be somewhere between 0 and 2.5V. This choice of capacitors does achieve this requirement. With this combination, lock is accomplished within a few seconds of switch on.

Again, I personally used a 32.000KHz crystal because I have several to hand. But a common 32.768KHz watch crystal is fine in this application too.

I am still COMPLETELY AMAZED that it is possible to stabilise a VFO, with a SINGLE cheap 74HC-series IC!